1. Field of the invention
The present invention relates to delayed-pulse generators and, more particularly, to a delayed-pulse generator In the form of a semiconductor integrated circuit.
2. Description of the Related Art
A conventional delayed-pulse generator of the type to which the present invention relates is shown in FIG. 1. The conventional generator comprises a current-mirror circuit 1 formed by PNP-type transistors Q1, Q2 and resistors R1, R2; a comparator circuit 2; a constant-current source 3 for setting an output current of the current-mirror circuit 1; a reference voltage source 4 connected to one input terminal of the comparator circuit 2, for setting a threshold voltage thereof; a capacitor C1 having one end grounded and the other end connected to the other input terminal of the comparator circuit 2 and charged by the output current from the current-mirror circuit 1; and an NPN-type transistor Q3 with the base thereof connected to a resistor R3, for discharging the charge in the capacitor C1.
The operation of this delayed-pulse generator will be described with reference to FIG. 2 which is a time chart illustrating the operation of the delayed-pulse generator. When an input pulse P.sub.IN applied to the base of the transistor Q3 through the resistor R3 changes its level from a high "H" to a low "L" at a predetermined timing, the transistor Q3 is turned off accordingly. As a result, the capacitor C1 starts to be charged by the output current I1 supplied from the current-mirror circuit 1, the value of the output current I1 being established by the constant-current source 3. With this charging of the capacitor C1, the potential at a node E is increased as shown in FIG. 2. When this voltage at the node E exceeds the threshold voltage V.sub.T of the comparator circuit 2 as set by the reference voltage source 4, the comparator circuit 2 operates to output an output pulse P.sub.OUT of "H" level at its output terminal T.sub.OUT.
The delay time (td) between the input pulse P.sub.IN and the output pulse P.sub.OUT can be expressed by the following Equation (1): EQU td=(C1.multidot.V.sub.T)/I1 (1)
where C1 represents the capacitance of the capacitor C1.
As can readily be understood from the above Equation (1) that, in order to obtain a long delay time, it is necessary to select a high capacitance for the capacitor C1 or set the charging current I1 small. Generally, it is difficult to make large the capacitance of the capacitor formed in an integrated circuit. The upper limit of the capacitance is about 30 pF, although it more or less depends on the chip area.
A case of realizing a long delay time with a low charging current I1 will now be described. Assuming that the capacitance C1 to be 30 pF and the reference voltage V.sub.T to be 3.0 V, for obtaining a delay time of 10 msec., the charging current I1 has to be set to a very small value of about 0.9 nA.
Here, there is flowing a leakage current I.sub.L3 in the switching transistor Q3 for the capacitor C1. When the junction temperature of the transistor Q3 is 25.degree. C., the leakage current is about 0.2 pA. However, it is doubled with each temperature rise by 8.degree..about.10.degree. C. and acts to subtract itself from the charging current I1 to flow into the capacitor C1. As a consequence, the delay time (td) is increased in accordance with the increase in the junction temperature as shown by the curve B in FIG. 3. At 125.degree. C., the leakage current I.sub.L3 is about 1 nA. This value is substantially the same as the value of the charging current I1 noted above. This means that, at the temperature of 125.degree. C., the charging current I1 towards the capacitor C1 from the current-mirror circuit 1 is consumed entirely as leakage current which flows in the transistor Q3. In this state, the capacitor C1 is not charged, so that the potential at the node E remains at 0 volt. Therefore, even where the "L" level input pulse P.sub.IN is applied to the input terminal T.sub.IN in this state, the comparator circuit 2 remains inoperative, and the desired output pulse P.sub.OUT is not provided.
As explained hereinabove, with the above conventional delayed-pulse generator, the capacitance of the capacitor in the integrated circuit cannot be made large and, for making the delay time long, it is necessary to set a small current value of the constant-current source. This means that in a high temperature operation the leakage current of the switching transistor makes it difficult to set a long delay time. Besides, the leakage current of the switching transistor eventually causes erroneous operation. These are problems in the conventional delayed-pulse generator to be solved.